Modern computer systems typically include a memory device which may be accessed and/or controlled by a control device such as a memory controller. The memory controller may communicate with the memory device via one or more busses. For example, the memory controller and the memory device may be coupled by a command bus and an address bus. The command bus is configured to provide one or more control signals to the memory device, while the address bus is configured to provide address signals to the memory device. As an example, in a given clock cycle, data may be read out from the memory device by transmitting, from the memory controller to the memory device, a plurality of control signals and address signals over the command bus and address bus, respectively. The input signals are then decoded by the memory device, after which the requested data is returned to the memory controller.
A given command or address is typically defined by a plurality of inputs propagated over the respective command bus (in the case of a command) or address bus (in the case of an address). Each input is provided to a corresponding pin on a respective interface of the memory device. Thus, a given command/address input combination in a given cycle may require N command inputs to N pins of a command bus interface on the memory device, and P address inputs to P pins of an address bus interface on the memory device.
One of the design considerations in manufacturing memory devices, is the number of input pins required to support the various combinations of commands and addresses. The greater the number of pins required, the larger and the more costly the resulting memory device is.
Therefore, there is a need for reducing the number of pins needed to interface a memory with a control device, such as a memory controller or processor).